More on the AMD Zen architecture

More on the AMD Zen architecture

Yesterday we wrote about the new AMD Zen architecture and we got into more details since we heard of this upcoming architecture for the first time ever. This was all thanks to a slide leak, possibly by AMD. Now the story continues due to a new leak that this time describes an entire multi-core CPU based on the Zen architecture.

The leak in the form of a slide can be found again on the German web site and like we said it shows a multi-core Zen processor. Just like a single Zen core the entire chip is a monolithic design and there are no shared resources like in Bulldozer. But there’s more – AMD will be able to create blocks made of Zen cores. The blocks are called “units” and each unit consists of four Zen cores. Each core has 512 KB of L2 cache while a single unit can access 8 MB of L3 cache, which means that a single core gets 2 MB of L3 cache on average. An interesting fact is that Zen will use an inclusive cache hierarchy, which means that the data that sits in the L1 cache will be copied and kept in the L2 cache. This is not the most efficient cache usage but Intel’s processors have been using this technology for decades while offering performance advantages. According to AMD the inclusive cache scheme will provide simplicity when building the cache as well as high performance and low latency. Finally the units will communicate via a high-speed interconnect link. Thanks to this same unit architecture AMD will be able to create various processors aimed at different market segments so expect four-core, eight-core and possibly twelve-core Zen processors for the desktop and server markets. The chips are expected to be built on 14 nm FinFET technology and will appear in 2016 providing native support for DDR4 thanks to an integrated DDR4 memory controller.


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